IEEE Fellow

As it stands today, the IEEE Grade of Fellow is conferred by the Board of Directors upon a person with an extraordinary record of accomplishments in any of the IEEE fields of interest. The total number selected in any one year does not exceed one-tenth of one percent of the total voting Institute membership. Each new Fellow receives a beautifully matted and framed certificate with the name of the Fellow and a brief citation describing the accomplishment, a congratulatory letter from the incoming IEEE president and a gold sterling silver Fellow lapel pin with an antique finish.

Please note: The list below includes "IEEE Fellows" elevated by the Council on Electronic Design Automation. The Council acknowledges that there are additional members of our community that have been elevated by other organizational units of the IEEE.

Nomination Details:

Fellow nominations are due February 7 each year.

Information on the IEEE Fellows Program to help nominators prepare their submissions.

Recipients

2023

Ryan Kastner

for contributions to the design and security of reconfigurable systems

Sung Kyu Lim

for contributions to electronic design automation and the tradeoff for 3-dimensional integrated circuits

2022

Yu Wang

for contributions to domain specific accelerator design

Mahesh Iyer

6 (Western U.S.)

Biography

Mahesh Iyer is an Intel Sr. Fellow and chief Electronic Design Automation (EDA) software and FPGA architect in the Programmable Solutions Group (PSG)/Datacenter and AI group. He is responsible for defining and carrying out the technical vision and direction for the Quartus compiler organization and its products with synergies in FPGA architecture design. Iyer’s technical leadership and innovations in overhauling Quartus algorithms and in co-designing with hardware architecture have played a significant role towards AgilexTM achieving fabric performance/watt leadership. Iyer mentors PSG’s university research programs and serves on Intel’s Corporate Research Council. Prior to Altera/Intel, Iyer served as the software architect and co-author for some of Synopsys' most successful EDA products, including Design Compiler, IC Compiler, and VCS. Iyer’s pioneering technical inventions and contributions in ASIC Electronic Design Automation (EDA) algorithms, flows, and methodologies have been productized in industry-leading EDA products that have been foundational to the semiconductor industry. Iyer earned a bachelor’s degree in electronics from the University of Bombay in India and a master’s degree and Ph.D. in electrical engineering from the Illinois Institute of Technology, which honored him with a Distinguished Alumni Professional Achievement Award in 2010. He currently serves on the external advisory board of the ECE department at the Illinois Institute of Technology. In 2017, Iyer completed the Executive Accelerator Program at Stanford University’s Graduate School of Business. Iyer has published approximately 40 papers on various EDA topics and has 90+ issued or pending patents in related fields. Iyer was named a Synopsys Fellow in 2006, an Altera Fellow in 2013, an Intel Fellow in 2016, and an Intel Sr. Fellow in 2021. Mahesh was elevated to IEEE Fellow for his leadership contributions to ASIC and FPGA Electronic Design Automation.

Affiliation(s)

Intel Sr. Fellow

Intel Corporation

United States

for leadership in ASIC and FPGA Electronic Design Automation

Puneet Gupta

for contributions to the design and co-optimization of integrated circuits

Luca Daniel

for contributions to modeling and simulation of electronic systems

Samarjit Chakraborty

for contributions to system-level timing analysis of cyber-physical systems

R. Iris Bahar

for contributions to modeling and design of power-aware and noise-tolerant nanoscale computing systems

2021

Mehdi Tahoori

For contributions to resilient nanoscale integrated circuits

Dmitri Maslov

For contributions to quantum circuit synthesis and optimization, and compiling for quantum computers